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ARAM - Audio RAM
THE WONDERFUL ART OF DOWNGRADED DRAM (ARAM)
By : Cecil Ho, CST, Inc http://www.simmtester.com/index.html 5/94.
General
I have traveled around the world promoting SIMM/Memory testers. One topic I frequently encounter is the nature
and the testing of ARAM. The term ARAM stands for Audio RAM. It is sometimes also called the Toy Grade RAM, the
Down Graded RAM or the Reduced Spec. RAM. Generally it points to the millions of memory chips that fail to meet
chip manufacturer's final testing stage but still are functionally good for some reduced specification applications.
With these memory chips at a fraction of the price, they are indeed a bargain if you know how to use and to take
advantage of them.
To test and qualify ARAM is not an exact science. There are no general procedures or specifications for testing
ARAM. Instead, ARAM must be selected to the application and tested to the application requirements. To further
complicate the issue, the user of these ARAMs usually cannot afford to use the same million dollar ATE memory
tester that the chip manufactures use. This article is intended to highlight the different ARAM applications and
the general method of testing for each application.
The three bit and two bit good DRAM
The standard 1MX32 SIMM module is usually made with 8 pieces of 1MX4 chips. However, this module can also be made
out of a combination of 8 pieces of 1MX3 chips and 4 pieces of 1MX2 chips. While 1MX3 chips and 1MX2 chips are
not standard chips, they are actually normal 1MX4 chips with either one or two of the bits testing bad. For example,
in semiconductor manufacturing most of the failed chips at the final test stage are either one or two bits bad
out of four bits.
Therefore, these two or three good bits can still be used to form 1MX2 chips and 1MX3 chips and these "created
chips" are now called either two bit or three bit good DRAM. When testing the 3 bit good chips, users usually
label the bad bits by the following selections. The "A" version means that bit 0 is bad, the "B" version means
bit 1 is bad, the "C" version means bit 2 is bad and the "D" version means that bit 3 is bad. This gives users
four straightforward selections for the 3 bit good chips: A, B, C, D. Two bit good chips then would have the
following six combinations: AB, AC, AD, BC, BD, and the CD.
For the 3 bit good chips there are four different versions of the SIMM module's PCB to accommodate the different
combinations of bad bits. The 2 bit chips in addition to having the four different versions of the SIMM module's
PCB also have a combination of 6 jumpers on the PCB. When testing for 3 bit and 2 bit good chips, high speed and
thorough tests have to be performed. The bit failure is contained in one bit chain and is usually only a few
cells deep.
A very severe test pattern is usually applied to uncover these bad cells. The commonly used test patterns are
the "Checker Board" and the "Marching" tests. In addition, "Page Mode Marching" or "EDO Marching" tests might be
needed. To ensure that the bad bit does not affect the rest of the chip's performance, cross talk test also has
to be performed. Since theory also points out that a massive failure on one bit could possibly contaminate the
other bits in some combinations, the rule of thumb is that the total number of failed cells has to be less than
0.05% of the total cells.
To further ensure the performance a noise margin test and DC parametric leakage test should also be performed.
Since these chips have not been through burn-in quality control in the normal semiconductor process, 72 hours of
temperature burn-in might be necessary to ensure the long term stability of these chips.
Upper and lower half good DRAM
In this category of ARAM, half the cells are bad in each one of the chip's 4 data bits. In other words, a 1MX4 chip
can be bad on all bits but still good as a 512KX4 chip.
In this case, the chip still can be used to build memory SIMMs. Instead of 8 pieces of 1MX4 chips to make up a
1MX32 module, it would now need 16 pieces of 512KX4 chips. At the same time, it would require a controller chip to
manipulate the highest address line and to switch between the two banks of half good chips. With 512KX4 chips,
there are two categories depending on whether or not the chip's address faults lie either on the upper half or
the lower half of the chip.
For the upper half good chip, it is generally coded as "half good H chips". For the lower half good chip, it is
coded as "half good L chips". The testing routine for these types of ARAM will need to have the capability to
identify these categories. The controller chip that allows selection between the two banks of half good chips are
generally made out of a dozen logic gates and are simple enough to be implemented with PAL (Programmable Array Logic).
To maintain the operational access time of the final SIMM module, the gate
delay of this PAL generally has to be under 7 nanoseconds. Pericom Semiconductor
has also integrated some of these SIMM controller functions monolithically
and is offering them at a much lower price than the regular PAL.
DRAM with known bad cell locations
In another case of ARAM, the DRAM in question may contain only a few bad
cells. If the address location of these bad cells are known and "marked",
it can be "made up" with SRAM cells.
This method is similar to the way Cache RAMs work in a computer system.
In a computer system, the Tag RAM marks the location of the memory cells
in the DRAM and replaces them with SRAM cells for faster access. In the
same way, if the bad cells in a DRAM is marked with an address table, the
address request can be redirected to a small block of SRAM cells. This will,
of course, involve a controller chip to perform all the bookkeeping functions.
This controller chip would be an ASIC combination of an address tag table,
a block of SRAM and the necessary logic to deliver the proper operation.
This method is usually executed on a SIMM module where all the faulty cells
are pretested and record onto the tag table through the Eprom programming
function on the ASIC. In this application, the marking of the bad cells
and the tracking of the chips to go onto the final SIMM module becomes a
major task. The test algorithm required on a tester for this type of ARAM
not only has to discover all address locations on the bad cells, it also
has to have a bookkeeping database, the stamp marking control and the capability
to track the chip through the module production line.
DRAM in TV game and toy applications
The quality of DRAM required in a TV game or toy application are much less
stringent and consequently can have more "flaws" than the other applications
we have mentioned so far. The DRAM used in a TV game or toy application
is usually contained on one chip. The TV game or toy application chip is
divided into 3 parts: the operating system part, the video part and the
audio part. Each TV game and toy is made up of a small microprocessor and
other interface circuits.
The microprocessor relies on the accuracy of the operating system program
to perform its task. Any mistake in this operating system will drive the
system into the "no brain land" or cause it to become "lost". Therefore,
the section of the memory dedicated to containing the microprocessor's operating
system has to be fault free. This requires about 10 to 25% of the chip.
Although the operating system part of the chip must be flawless, the other
parts - video and audio, can contain error. For example, the video part,
also known as the picture, on TV games have random pixel voids. These pixel
voids block out the picture causing black dots on the picture.
Most of the time, however, these voids cannot be detected by the normal
human eye, so it is okay on the DRAM to have some flaws in the video portion
of the game. The only time these pixel voids are unacceptable are when several
void pixels group together causing major picture blockage. Lastly, the audio
part portion on a video game or toy definitely does not have to be perfect.
Cracks, pops and other sound distortion in a game's sound track are often
tolerated. To successfully test game and toy DRAM, a tester needs to have
an algorithm that can isolate a block of good cells for the operating system,
a large block of cells that has only isolated single cell error for the
video part and lastly for the audio part be able to detect the rest of the
cells that can have random bad cells as long as they are not cluttered together.
DRAM in answering machine and voice recorders
The new generation of the digital answering machine and voice recorder consist
of a DSP (digital signal processor) and a bank of DRAM. While the DSP fulfills
the control function and the signal processing A/D function, the DRAM records
the message in a compressed digital format. Depending on the coding and
decoding format, the requirement on the DRAM are different. In general,
when dealing with these types of DRAM there are two types of flaws that
can occur.
The first is cross cell contamination, also known as cross talk. Cross cell
contamination causes audio echoes in an answering machine. The other flaw
is when two consecutive cells fail on a bit. It is permissible for single
cell failure but two consecutive cell failures causes extreme message distortion.
In order to test these DRAMs, a tester needs an algorithm that can address
these problems.
DRAM in CD audio players
A CD audio player uses DRAM memory to buffer its audio to allow it to recover
from shocks and pops.
This application of DRAM is very similar to the digital answering machine
application outlined earlier. Due to the high fidelity requirement of the
audio channel, usually 15 bits of a 16 bit word is used for the digitized
audio content. A word is an audio sampling. The 16th bit is usually used
for parity checking. This parity system works by recording the check sum
of the 15 bits to see if any bad cells exist. So the 16th bit is the parity
bit. By checking the 16th bit, the DSP (digital signal processor) will know
if it needs to normalize the peaks and pops on the audio. However, if the
15 bits have two consecutive bad cells instead of one, the parity bit will
be wrong.
This occurs because the parity bit is only set up to recognize one bad bit
not two consecutive bits. It will not be able to detect and normalize the
audio. It is, therefore, very important that all the consecutive bad locations
are found and discriminated. Since most cell failures in DRAM are located
in a group of cells, the possibility of consecutive bad cells are more than
the manufacturer wants. In order to solve this problem, the DSP is usually
built-in with address scrambling options to reverse the address lines. Thus
any consecutive bad cells will be broken out into more separated bad cells
instead of clutters.
The tester for this DRAM not only has to be able to detect consecutive bad
cells, it also has to have the capability to mathematically calculate the
spread locations of the bad cells under the address scrambling mode. With
this capability, it will be able to determine if the DRAM is suitable for
the application.
Automated testing for ARAMs
ARAM applications are usually high volume and low budget projects so the
only viable way to test them is through automation. Therefore, an automatic
chip handler is necessary. Due to the quantity being tested, multi-site
testing also is needed. A parallel tester and a 4 site handler are the best
combination in terms of low cost and high throughput. Since the application
requires a maximum of 6 different output types, an 8 site output would also
be a good choice.
Conclusion
With the worldwide demand and the continued expansion of DRAM manufacturing,
more applications and requirements for ARAM will surface. CST, Inc. is committed
to the research of this subject, not only by bringing you the latest information,
but also by providing the best memory tester and automated chip handler for the job.
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