clock / multiplier locking
Intel Pentium Classic 133 (P54C)
2.5x & 3.0x
P54C-133 S-Spec of S106J has the 2.5 & 3.0x multiplier disabled
Pentium 133 SY022 wouldn't recognize any multiplier setting higher than x2
Intel PentiumMMX 166 (P55C)
3x & 3.5x
By manufacturing date
Pentium MMX-166s with the 3x and 3.5x multipliers disabled: from Mid-July 1997 (27th week of the year) on
PGA Educated Guess method
Pentium with plastic PGA have the 3x and 3.5x multipliers enabled, where as the ones with the ceramic PGA don't, but this isn't always true.
Manufacturing Info. method
If the plant code is L, that chip was made in Malaysia, which are supposed to be more overclockable and more likely to have the 3x and 3.5x multipliers enabled than those made in the Philippines, which has the plant code E.
If the s-Spec is SL27H, the serial number begins with L, and the serial number is L7263371-0219 or older, then the chip has the 3x and 3.5x multipliers enabled.
If the s-Spec is SL27H, the serial number begins with L, and the serial number is L7270651-1052 or newer, then it was manufactued using a different fab. process, and the 3x and 3.5x multipliers are disabled.
If the s-Spec is SL27H and the serial number begins with C, then it's from the original fab. process, and the 3x and 3.5x multipliers are enabled.
If the s-Spec is SL27H and the serial number begins with any other letter, your guess is as good as mine.
If the s-Spec is SL27K, chips manufactured before the 27th week of 1997 (i.e. 87260031-1437) had the 3x and 3.5x multipliers enabled, but later versions (27th week and afterwards) have the 3x and 3.5x multipliers disabled.
If the s-Spec is SY059, as far as I know they all support the 3x multiplier, but only some support the 3.5x multiplier. This is appearantly the result of being manufactured on a line before the 233 was developed. See P200MMX info for details.
Any other s-Specs, your guess is as good as mine.
Intel PentiumMMX 200 (P55C)
Old Pentium MMX 200s that were manufactured before 233s were (when 200
was top-of-the-line), don't support the 3.5x multiplier since that was designed
for the Pentium MMX 233. One way to tell the old ones from the new
is by the manufacturing stepping. The old ones had a mfg. stepping
of xA3 (SL23S/stepping of 4), and the new ones have a mfg. stepping of xB1
(SL27K/stepping of 3).
Intel Pentium II
It seems that starting in mid-October 1997, due to extremely high yields
(meaning that practically every Pentium MMX produced now is capable of running
at 233MHz and every Pentium II produced now is capable of running at 300MHz
perfectly fine), Intel is making these processors with their multipliers
disabled by not bonding them. In other words, because all of the CPUs
Intel is making now can run at top-of-the-line speed, they are disabling
multipliers higher than intended to prevent people from spending less money
Clock locking on intel Pentium
This is done by internally hard wiring BF0 or BF1 without respect to any user defined setting.
On P54C versions [CPU ID 5-2-x] a BF1 pin permanently set to high (1) leads to multipliers of 1.5x and 2.0x only.
On P55C versions [CPU ID 5-4-x] a BF0 pin permanently set to low (0) leads to multipliers of 2.0x and 2.5x only.
Early P55C versions [CPU ID 5-4-0..2] still use BF0 / BF1 scheme of P54C releases. These CPU's are unaware of 3.5x multipliers but not locked.
To disable these clock locking mechanisms you'll have set BF0 / BF1 manually by manipulating either the CPU socket or the CPU pins itself. This is in no way recommended. An easier way to reach higher CPU speeds is to raise the bus clock speed. Most mainboards offer FSB of 75 / 83MHz which can be used with most Pentium P55C. (Editors note: A standard P166MMX runs 2.5x66 = 166MHz while 2.5x 75 = 188MHz and 2.5x 83 = 208MHz are possible)
Clock locking on intel Pentium II
That pretty much leaves one way to lock down the multiplier: put a circuit on the Slot 1 PCB that sits between the chipset and the CPU pins. The lock circuit could sit there, invisible to the entire system during normal operation. As long as RESET# is inactive, it could let the signals on A20M#, IGNNE#, LINT and LINT pass without interference. The lock circuit would listen to the RESET# pin; upon hearing it go active, it would kick into action. It would have to block any signal coming from the chipset onto A20M#, IGNNE#, LINT and LINT and impose its own, fixed multiplier on those pins until RESET# goes inactive again.
Clock locking on intel Pentium III
The fact that the PIII core is not locked to a specific speed, but to a range of speeds, shows that my concerns about the feasibility of building an on-die, temperature-independent bus lock were justified. For those of you who read the earlier article, you'll recall that I stated that any bus-locking scheme implemented on-die would run into heat-related accuracy problems. This appears to be the case on the PIII, though they've got the accuracy problem under control enough to make an on-die bus lock feasible. I have some insight on how Intel might have accomplished this task.
Clock locking on intel Xeon
Intel has a pretty sane way of providing the consumer some protection against buying remarked, overclocked Xeons. Each Xeon has a processor information ROM (PIROM) built into the processor substrate. This PIROM is electrically programmed at the factory to hold details about the chipís core type, core stepping, etc. There are 16 bits at offset 16h in the PIROM that store the processors maximum core frequency (in MHz). So if you want to know what the speed your Xeon was rated at, just check that number.